This invention relates to manufacturing methods for semiconductor devices, particularly those used in insulated gate bipolar transistors (IGBT) and static induction (SI) thyristors.
In recent years attention has been focussed on IGBT and SI thyristors as large power switching devices. These semiconductor devices are described below with reference to the drawings.
FIG. 1 is a cross-sectional view showing the construction of an IGBT element. High impurity concentration n.sup.+ buffer layer 13 is formed on high impurity concentration p.sup.+ type semiconductor substrate 12 which is provided with anode electrode (collector electrode) 11. Low impurity concentration n.sup.- type semiconductor layer 14 is formed on n.sup.+ buffer layer 13, p type impurity regions 15 are formed in the surface region of n.sup.- type semiconductor layer 14, and high impurity concentration n.sup.+ type impurity regions 16 are formed in these p type impurity regions 15. Cathode electrodes (emitter electrodes) 17 are provided on these p type impurity regions 15 and n.sup.+ type impurity regions 16. Also, gate electrode 19 is formed on surfaces of p type impurity region 15 and n.sup.- type semiconductor layer 14 with gate insulating film 18 interposed.
FIG. 2 is a cross-sectional view showing the construction of a SI thyristor element. In the same way as in the IGBT in FIG. 1, high impurity concentration n.sup.+ buffer layer 23 and low impurity concentration n.sup.- type semiconductor layer 24 are formed on high impurity concentration p.sup.+ type semiconductor substrate 22 which is provided with anode electrode 21. Also, high impurity concentration p.sup.+ type impurity regions 25, which function as the gate and high impurity concentration n.sup.+ type impurity region 26, are formed by thermal diffusion in the surface region of n.sup.- type semiconductor layer 24. Cathode electrode 27 is provided on n.sup.+ type impurity region 26, and insulating films 28 are formed on p.sup.+ impurity regions 25.
These semiconductor devices can cut off the main current flowing through the device by gate control. Characteristically the current density of these devices can be made higher than in an MOS FET, in which only majority carriers contribute to the current, since n.sup.- type semiconductor layers 14 or 24 cause conductivity modulation by minority carriers (holes) which are injected in high-resistance n.sup.- type semiconductor layers 14 or 24 from p.sup.+ type semiconductor substrates 12 or 22 through buffer layers 13 or 23. Moreover, when compared with bipolar transistors, it is known that, as well as high-speed switching being possible, there being less lost power and there being high breakdown voltage, there is also low ON resistance. However, there are some incompatible characteristics of these devices. For example, there is a trade-off relationship between high-speed switching and the production of low ON resistance. To improve this trade-off, that is to achieve low ON resistance as well as high-speed switching, it is necessary to form thin high impurity concentration n.sup.+ buffer layers 13 and 23.
The manufacturing method for the IGBT shown in FIG. 1 will be described with reference to FIG. 3(a) to FIG. 3(c). The same symbols are used in FIG. 3 where applicable.
First, as shown in FIG. 3(a), thin high impurity concentration n.sup.+ buffer layer 13, in which phosphorus (P) is typically the dopant, is formed by expitaxial growth on high impurity concentration p.sup.+ type semiconductor substrate 12. Low impurity concentration n.sup.- type semiconductor layer 14, in which phosphorus (P) is the dopant, is formed by expitaxial growth on n.sup.+ buffer layer 13. Next, as shown in FIG. 3(b), p type impurity regions 15 are formed in the surface portion of this n.sup.- semiconductor layer 14 by thermal diffusion, and then n.sup.+ type regions 16 are formed in the surface portion of these p type impurity regions 15 by thermal diffusion. At the same time, the phosphorus in n.sup.+ buffer layer 13 diffuses into n.sup.- type semiconductor layer 14. After this, gate insulating film 18 and gate electrode 19 are formed on surfaces of p type impurity region and n.sup.- type semiconductor layer 14. Furthermore, anode electrode 11 is provided on semiconductor substrate 12, and cathode electrodes 17 are provided on p type impurity regions 15 and n.sup.+ type impurity regions 16. FIG. 3(c) shows the impurity profile of the semiconductor device of FIG. 3(b).
In this process, assuming the diffusion coefficient of the dopant in n.sup.+ buffer layer 13 is large, forming p type impurity regions 15 and n.sup.+ type impurity regions 16 (in the SI thyristor, p.sup.+ type impurity regions 25 and n.sup.+ impurity regions 26) in the surface region of n.sup.- type semiconductor layer 14 by thermal diffusion causes the dopant of n.sup.+ buffer layer 13 to also be diffused and thus a thin high impurity concentration n.sup.+ buffer layer 13 is not obtained. Therefore, when a dopant with a large diffusion factor, such as phosphorus, is used, both high-speed and low ON resistance cannot be achieved.
On the other hand, if the dopant of n.sup.+ buffer layer 13 is arsenic (As), antimony (Sb) or bismuth (Bi) which have small diffusion coefficients, the dopant (for example boron (B)) of the p.sup.+ type semiconductor substrate 12 will have a larger diffusion coefficient than any of these dopants. For this reason, significant mutual diffusion of the dopant of n.sup.+ buffer layer 13 and the dopant of p.sup.+ type semiconductor substrate 12 occurs due during the thermal diffusion process. Therefore, reduction of the concentration in n.sup.+ buffer layer 13, disappearance of the n.sup.+ buffer layer 13 which depends on the diffusion time, and diffusion of the impurities of p.sup.+ type semiconductor substrate 12 to the n.sup.- semiconductor layer 14 can occur. Even if impurities with small diffusion coefficients are used as dopants of the n.sup.+ buffer layer 13, a thin high concentration n.sup.+ buffer layer 13 still cannot be obtained.
As a result, in the semiconductor manufacturing method described above, a thin high concentration buffer layer is extremely difficult to form. Consequently semiconductor devices which have both high speed switching and also low ON resistance cannot be produced.